Vol. E91-C, No. 4 April 2008

Published: 2008-04-01

Foreword

FOREWORD

Masao NAKAYA

399-399
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Letters

An Ultra-Low-Voltage Ultra-Low-Power Weak Inversion Composite MOS Transistor: Concept and Applications

Luis H.C. FERREIRA, Tales C. PIMENTA, Robson L. MORENO

662-665
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High-Input and Low-Output Impedance Voltage-Mode Universal DDCC and FDCCII Filter

Hua-Pin CHEN, Wan-Shing YANG

666-669
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A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters

Kicheol KIM, Youbean KIM, Incheol KIM, Hyeonuk SON, Sungho KANG

670-672
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Papers

A Low-Power Instruction Issue Queue for Microprocessors

Shingo WATANABE, Akihiro CHIYONOBU, Toshinori SATO

400-409
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Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems

Makoto SUGIHARA, Tohru ISHIHARA, Kazuaki MURAKAMI

410-417
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Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems

Hamid NOORI, Maziar GOUDARZI, Koji INOUE, Kazuaki MURAKAMI

418-431
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Power-Aware Compiler Controllable Chip Multiprocessor

Hiroaki SHIKANO, Jun SHIRAKO, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA

432-439
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Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm

Yibo FAN, Takeshi IKENAGA, Satoshi GOTO

440-448
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A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems

Qin LIU, Seiichiro HIRATSUKA, Kazunori SHIMIZU, Shinsuke USHIKI, Satoshi GOTO, Takeshi IKENAGA

449-456
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A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition

Yuichiro MURACHI, Yuki FUKUYAMA, Ryo YAMAMOTO, Junichi MIYAKOSHI, Hiroshi KAWAGUCHI, Hajime ISHIHARA, Masayuki MIYAMA, Yoshio MATSUDA, Masahiko YOSHIMOTO

457-464
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A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer

Yuichiro MURACHI, Junichi MIYAKOSHI, Masaki HAMAMOTO, Takahiro IINUMA, Tomokazu ISHIHARA, Fang YIN, Jangchung LEE, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO

465-478
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Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling

Masanori HARIYAMA, Naoto YOKOYAMA, Michitaka KAMEYAMA

479-486
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Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems

Nicola E. L' INSALATA, Sergio SAPONARA, Luca FANUCCI, Pierangelo TERRENI

487-496
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A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions

Hamid NOORI, Farhad MEHDIPOUR, Koji INOUE, Kazuaki MURAKAMI

497-508
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Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing

Akihiro NAKAMURA, Masahide KAWARASAKI, Kouta ISHIBASHI, Masaya YOSHIKAWA, Takeshi FUJINO

509-516
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Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment

Hasitha Muthumala WAIDYASOORIYA, Weisheng CHONG, Masanori HARIYAMA, Michitaka KAMEYAMA

517-525
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A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model

Shinya KAJIYAMA, Ken'ichiro SONODA, Kazuo OTSUGA, Hideaki KURATA, Kiyoshi ISHIKAWA

526-533
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FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction

Shin-ichi O' UCHI, Meishoku MASAHARA, Kazuhiko ENDO, Yongxun LIU, Takashi MATSUKAWA, Kunihiro SAKAMOTO, Toshihiro SEKIGAWA, Hanpei KOIKE, Eiichi SUZUKI

534-542
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A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing

Hiroki NOGUCHI, Yusuke IGUCHI, Hidehiro FUJIWARA, Shunsuke OKUMURA, Yasuhiro MORITA, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO

543-552
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Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array

Tadayoshi ENOMOTO, Suguru NAGAYAMA, Hiroaki SHIKANO, Yousuke HAGIWARA

553-561
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Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)

Kenta YAMADA, Noriaki ODA

562-570
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Redundant Vias Insertion for Performance Enhancement in 3D ICs

Xu ZHANG, Xiaohong JIANG, Susumu HORIGUCHI

571-580
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Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling

Kazuyasu MIZUSAWA, Naoya ONIZAWA, Takahiro HANYU

581-588
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Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation

Masatomo MIURA, Takahiro HANYU

589-594
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Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network

Hyunjeong PARK, Hyungsoo KIM, Jun So PAK, Changwook YOON, Kyoungchoul KOO, Joungho KIM

595-606
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TM Plane Wave Reflection and Transmission from a One-Dimensional Random Slab

Yasuhiko TAMURA

607-614
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Design Method for a Low-Profile Dual-Shaped Reflector Antenna with an Elliptical Aperture by the Suppression of Undesired Scattering

Yoshio INASAWA, Shinji KURODA, Kenji KUSAKABE, Izuru NAITO, Yoshihiko KONISHI, Shigeru MAKINO, Makio TSUCHIYA

615-624
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Planar T-Shaped Monopole Antenna for WLAN/WiMAX Applications

Jhin-Fang HUANG, Shih-Huang WU

625-630
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Characterization of Two-Stage Composite Right- and Left-Handed Transmission Lines

Shun NAKAGAWA, Koichi NARAHARA

631-637
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Computer Simulation about Temperature Distribution of an EM-Wave Absorber Using a Coupled Analysis Method

Shinya WATANABE, Akitoshi TANIGUCHI, Kota SAITO, Osamu HASHIMOTO, Toshifumi SAITO, Hiroshi KURIHARA

638-646
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Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis

Masakazu AOKI, Shin-ichi OHKAWA, Hiroo MASUDA

647-654
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A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI

Yusuke OHTOMO, Hiroshi KOIZUMI, Kazuyoshi NISHIMURA, Masafumi NOGAWA

655-661
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