A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI

Authors

  • Yusuke OHTOMO
  • Hiroshi KOIZUMI
  • Kazuyoshi NISHIMURA
  • Masafumi NOGAWA

Published

2008-04-01

Issue

Section

Papers