A 0.3-V Operating, <I>V</I><SUB>th</SUB>-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Authors

• Yasuhiro MORITA
• Hidehiro FUJIWARA
• Hiroki NOGUCHI
• Kentaro KAWAKAMI
• Junichi MIYAKOSHI
• Shinji MIKAMI
• Koji NII
• Hiroshi KAWAGUCHI
• Masahiko YOSHIMOTO