A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture

Authors

  • Junichi MIYAKOSHI
  • Yuichiro MURACHI
  • Tetsuro MATSUNO
  • Masaki HAMAMOTO
  • Takahiro IINUMA
  • Tomokazu ISHIHARA
  • Hiroshi KAWAGUCHI
  • Masayuki MIYAMA
  • Masahiko YOSHIMOTO

Published

2006-12-01