Vol. E90-C, No. 6 June 2007

Published: 2007-06-01

Foreword

FOREWORD

Tetsuya IIDA

1141-1141
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Letters

A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System

Yohei FUKUMIZU, Naoki GOCHI, Makoto NAGATA, Kazuo TAKI

1299-1303
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A Study to Realize a 1-V Operational Passive Σ-Δ Modulator by Using a 90 nm CMOS Process

Toru CHOI, Tatsuya SAKAMOTO, Yasuhiro SUGIMOTO

1304-1306
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Evaluation of Digitally Controlled PLL by Clock-Period Comparison

Yukinobu MAKIHARA, Masayuki IKEBE, Eiichi SANO

1307-1310
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A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter

Philipus Chandra OH, Akira MATSUZAWA, Win CHAIVIPAS

1311-1314
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A High Impedance Current Source Using Active Resistor

Takeshi KOIKE, Hiroki SATO, Akira HYOGO, Keitaro SEKINE

1315-1317
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Papers

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

Young-Chan JANG, Jun-Hyun BAE, Sang-Hune PARK, Jae-Yoon SIM, Hong-June PARK

1156-1164
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The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time

Masaya MIYAHARA, Akira MATSUZAWA

1165-1171
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Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC

Yusuke IKEDA, Akira MATSUZAWA

1172-1180
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A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm

Hao SAN, Yoshitaka JINGU, Hiroki WADA, Hiroyuki HAGIWARA, Akira HAYAKAWA, Haruo KOBAYASHI, Tatsuji MATSUURA, Kouichi YAHAGI, Junya KUDOH, Hideo NAKANE, Masao HOTTA, Toshiro TSUKADA, Koichiro MASHIKO, Atsushi WADA

1181-1188
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On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration

Koichiro NOGUCHI, Takushi HASHIDA, Makoto NAGATA

1189-1196
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An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter

Shiro DOSHO, Naoshi YANAGISAWA, Kazuaki SOGAWA, Yuji YAMADA, Takashi MORIE

1197-1202
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An Active Terminal Circuit and Its Application to a Distributed Amplifier

Hitoshi HAYASHI, Munenari KAWASHIMA, Tadao NAKAGAWA, Kazuhiro UEHARA, Yoshihiro TAKIGAWA

1203-1208
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IM3 Cancellation Method Using Current Feedback Suitable for a Multi-Stage RFIC Amplifier

Toshifumi NAKATANI, Koichi OGAWA

1209-1221
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Miniaturized Broadband Lumped-Element In-Phase Power Dividers

Hitoshi HAYASHI, Tadao NAKAGAWA, Kazuhiro UEHARA, Yoshihiro TAKIGAWA

1222-1227
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A SiGe BiCMOS VCO IC with Highly Linear Kvco for 5-GHz-Band Wireless LANs

Satoshi KURACHI, Toshihiko YOSHIMASU, Haiwen LIU, Nobuyuki ITOH, Koji YONEMURA

1228-1233
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A New Inductor-Less IP2 Enhancement Technique for CMOS Multi-Standard Mixer

Mohammad B. VAHIDFAR, Omid SHOAEI

1234-1240
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A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage

Toshiya MITOMO, Osamu WATANABE, Ryuichi FUJIMOTO, Shunji KAWAGUCHI

1241-1246
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A Fast f_c Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems

Osamu WATANABE, Rui ITO, Shigehito SAIGUSA, Tadashi ARAI, Tetsuro ITAKURA

1247-1252
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Design of a New Folded Cascode Op-Amp Using Positive Feedback and Bulk Amplification

Mohsen ASLONI, Khayrollah HADIDI, Abdollah KHOEI

1253-1257
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A Current-Mode, First-Order Takagi-Sugeno-Kang Fuzzy Logic Controller, Supporting Rational-Powered Membership Functions

Mahdi MOTTAGHI- KASHTIBAN, Abdollah KHOEI, Khayrollah HADIDI

1258-1266
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Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling

Akira TSUCHIYA, Masanori HASHIMOTO, Hidetoshi ONODERA

1267-1273
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Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver

Takeshi KUBOKI, Akira TSUCHIYA, Hidetoshi ONODERA

1274-1281
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Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements

Kouji ICHIKAWA, Yuki TAKAHASHI, Makoto NAGATA

1282-1290
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Automated Design of Analog Circuits Accelerated by Use of Simplified MOS Model and Reuse of Genetic Operations

Naoyuki UNNO, Nobuo FUJII

1291-1298
- Requires Subscription PDF
Influence of Residual Stress on Post-Fabrication Resonance Wavelength Trimming of Long-Period Fiber Gratings by Heating

Katsumi MORISHITA, Akihiro KAINO

1318-1323
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Characteristics of an Optical Filter Composed of Two Vertically Coupled Microring Resonators

Hiroyuki OKAMOTO, Masanobu HARAGUCHI, Toshihiro OKAMOTO, Masuo FUKUI

1324-1328
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Study on Transmission Characteristics of Transformers of a RF Splitter

Tomohiko KANIE, Hiroaki KATO, Yuichi NORO, Takashi TAKEO, Kiwamu ODA, Haruhiko ITO

1329-1335
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Design of a CMOS Heartbeat Spike-Pulse Detection Circuit Integrable in an RFID Tag for Heart Rate Signal Sensing

Toshitaka YAMAKAWA, Takahiro INOUE, Masayuki HARADA, Akio TSUNEDA

1336-1343
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Invited Papers

Challenges in Designing CMOS Wireless Systems-on-a-Chip

Masoud ZARGARI, David SU

1142-1148
- Requires Subscription PDF
Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

Atsushi IWATA, Takeshi YOSHIDA, Mamoru SASAKI

1149-1155
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Vol. E90-C, No. 6 June 2007

Foreword

FOREWORD

Letters

A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System

A Study to Realize a 1-V Operational Passive Σ-Δ Modulator by Using a 90 nm CMOS Process

Evaluation of Digitally Controlled PLL by Clock-Period Comparison

A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter

A High Impedance Current Source Using Active Resistor

Papers

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time

Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC

A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm

On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration

An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter

An Active Terminal Circuit and Its Application to a Distributed Amplifier

IM3 Cancellation Method Using Current Feedback Suitable for a Multi-Stage RFIC Amplifier

Miniaturized Broadband Lumped-Element In-Phase Power Dividers

A SiGe BiCMOS VCO IC with Highly Linear Kvco for 5-GHz-Band Wireless LANs

A New Inductor-Less IP2 Enhancement Technique for CMOS Multi-Standard Mixer

A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage

A Fast f_c Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems

Design of a New Folded Cascode Op-Amp Using Positive Feedback and Bulk Amplification

A Current-Mode, First-Order Takagi-Sugeno-Kang Fuzzy Logic Controller, Supporting Rational-Powered Membership Functions

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling

Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver

Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements

Automated Design of Analog Circuits Accelerated by Use of Simplified MOS Model and Reuse of Genetic Operations

Influence of Residual Stress on Post-Fabrication Resonance Wavelength Trimming of Long-Period Fiber Gratings by Heating

Characteristics of an Optical Filter Composed of Two Vertically Coupled Microring Resonators

Study on Transmission Characteristics of Transformers of a RF Splitter

Design of a CMOS Heartbeat Spike-Pulse Detection Circuit Integrable in an RFID Tag for Heart Rate Signal Sensing

Invited Papers

Challenges in Designing CMOS Wireless Systems-on-a-Chip

Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices

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