Vol. E89-C, No. 11 November 2006

Published: 2006-11-01

Foreword

FOREWORD

Takahiro HANYU

1491-1491
- Requires Subscription PDF

Letters

A Low-Power Write Driver for Hard Disk Drives

Tatsuya KAWASHIMO, Hiroki YAMASHITA, Masayoshi YAGYU, Fumio YUKI

1670-1673
- Requires Subscription PDF
A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications

Yeong-Kang LAI, Lien-Fei CHEN, Jian-Chou CHEN, Chun-Wei CHIU

1674-1675
- Requires Subscription PDF
Wave Absorber Formed by Arranging Cylindrical Bars at Intervals for Installing between ETC Lanes

Kouta MATSUMOTO, Takeru OZAWA, Takuya NAKAMURA, Takahiro AOYAGI, Osamu HASHIMOTO, Takashi MIYAMOTO

1700-1703
- Requires Subscription PDF
High Efficiency Open Collector Adaptive Bias SiGe HBT Differential Power Amplifier

Kuei-Cheng LIN, Tsung-Yu YANG, Kuan-Yu CHEN, Hwann-Kaeo CHIOU

1704-1707
- Requires Subscription PDF
Mode Converter Optimization for U-Style Rotary Joint

Dong-Hyun KIM, Jeong-Woo JWA, Doo-Yeong YANG

1708-1712
- Requires Subscription PDF
Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems

Wenliang TSENG, Chien-Nan Jimmy LIU, Chauchin SU

1713-1718
- Requires Subscription PDF

Papers

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design

Takayuki GYOHTEN, Fukashi MORISHITA, Isamu HAYASHI, Mako OKAMOTO, Hideyuki NODA, Katsumi DOSAKA, Kazutami ARIMOTO, Yasutaka HORIBA

1519-1525
- Requires Subscription PDF
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_th) Variation

Hiroyuki YAMAUCHI, Toshikazu SUZUKI, Yoshinobu YAMAGAMI

1526-1534
- Requires Subscription PDF
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs

Kenji SHIMAZAKI, Makoto NAGATA, Mitsuya FUKAZAWA, Shingo MIYAHARA, Masaaki HIRATA, Kazuhiro SATOH, Hiroyuki TSUJIKAWA

1535-1543
- Requires Subscription PDF
Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond

Noriaki ODA, Hiroyuki KUNISHIMA, Takashi KYOUNO, Kazuhiro TAKEDA, Tomoaki TANAKA, Toshiyuki TAKEWAKI, Masahiro IKEDA

1544-1550
- Requires Subscription PDF
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification

Masanori HARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA

1551-1558
- Requires Subscription PDF
Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise

Mitsuya FUKAZAWA, Makoto NAGATA

1559-1566
- Requires Subscription PDF
High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique

Ching-Yuan YANG, Meng-Ting TSAI

1567-1574
- Requires Subscription PDF
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic

Naoya ONIZAWA, Takahiro HANYU

1575-1580
- Requires Subscription PDF
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach

Yohei FUKUMIZU, Makoto NAGATA, Kazuo TAKI

1581-1590
- Requires Subscription PDF
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Takahiro HANYU

1591-1597
- Requires Subscription PDF
Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing

Tomohiro TAKAHASHI, Takahiro HANYU

1598-1604
- Requires Subscription PDF
Vision Chip Architecture for Detecting Line of Sight Including Saccade

Junichi AKITA, Hiroaki TAKAGI, Takeshi NAGASAKI, Masashi TODA, Toshio KAWASHIMA, Akio KITAGAWA

1605-1611
- Requires Subscription PDF
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC

Hideyuki NODA, Katsumi DOSAKA, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Fukashi MORISHITA, Kazutami ARIMOTO

1612-1619
- Requires Subscription PDF
Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic

Michitaka OKUNO, Shinji NISHIMURA, Shin-ichi ISHIDA, Hiroaki NISHI

1620-1628
- Requires Subscription PDF
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing

Junichi MIYAKOSHI, Yuichiro MURACHI, Tomokazu ISHIHARA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO

1629-1636
- Requires Subscription PDF
A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory

Kan'ya SASAKI, Takashi MORIE, Atsushi IWATA

1637-1644
- Requires Subscription PDF
Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic

Naofumi HOMMA, Takafumi AOKI, Tatsuo HIGUCHI

1645-1654
- Requires Subscription PDF
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates

Masanori HARIYAMA, Sho OGATA, Michitaka KAMEYAMA

1655-1661
- Requires Subscription PDF
CMOS Image Sensor Using Negative-Feedback Resetting to Obtain Variably Smoothed Images

Masayuki IKEBE, Keita SAITO

1662-1669
- Requires Subscription PDF
Error Analysis of the Multilevel Fast Multipole Algorithm

Shinichiro OHNUKI, Weng Cho CHEW

1676-1681
- Requires Subscription PDF
Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL

Masaru KOKUBO, Takashi KAWAMOTO, Takashi OSHIMA, Takayuki NOTO, Masato SUZUKI, Shigeyuki SUZUKI, Takashi HAYASAKA, Tomoaki TAKAHASHI, Jun KASAI

1682-1688
- Requires Subscription PDF
Autonomous di/dt Control of Power Supply for Margin Aware Operation

Toru NAKURA, Makoto IKEDA, Kunihiro ASADA

1689-1694
- Requires Subscription PDF
Calculation of Measurement Uncertainties of Synchronously Sampled AC Signals in Nonideal Synchronization with Fundamental Frequency

Predrag PETROVIC

1695-1699
- Requires Subscription PDF

Invited Papers

Solid-Electrolyte Nanometer Switch

Naoki BANNO, Toshitsugu SAKAMOTO, Noriyuki IGUCHI, Hisao KAWAURA, Shunichi KAERIYAMA, Masayuki MIZUNO, Kozuya TERABE, Tsuyoshi HASEGAWA, Masakazu AONO

1492-1498
- Requires Subscription PDF
Carbon Nanotube Technologies for LSI via Interconnects

Yuji AWANO

1499-1503
- Requires Subscription PDF
Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions

Yoshihito AMEMIYA

1504-1511
- Requires Subscription PDF
Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture

Toru SHIMIZU, Masami NAKAJIMA, Masahiro KAINAGA

1512-1518
- Requires Subscription PDF