Vol. E89-C, No. 6 June 2006

Published: 2006-06-01

Foreword

FOREWORD

Tsuneo TSUKAHARA

663-663
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Letters

A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications

Yasuhiro SUGIMOTO, Yuji GOHDA, Shigeto TANAKA

811-813
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A Technique to Reduce Power Consumption for a Linear Transconductor

Fujihiko MATSUMOTO, Isamu YAMAGUCHI, Akira YACHIDATE, Yasuaki NOGUCHI

814-818
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Design of Analog Current-Mode Loser-Take-All Circuit

Mohsen ASLONI, Abdollah KHOEI, Khayrollah HADIDI

819-822
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Reduction of the Intensity Noise by Electric Positive and Negative Feedback in Blue-Violet InGaN Semiconductor Lasers

Minoru YAMADA, Kazushi SAEKI, Eiji TERAOKA, Yuji KUWAMURA

858-860
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Improvements in the Design of Matrix Distributed Amplifiers

Emad HAMIDI, Mahmoud MOHAMMAD- TAHERI

861-864
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Novel First-Order Non-inverting and Inverting Output of All-Pass Filter at the Same Configuration Using ICCII

Hua-Pin CHEN, Ming-Tzau LIN, Wan-Shing YANG

865-867
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A CMOS Built-In Current Sensor for IDDQ Testing

Jeong Beom KIM, Seung Ho HONG

868-870
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Papers

A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications

Vahid MAJIDZADEH, Omid SHOAEI

692-701
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Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit

Masayuki UNO, Shoji KAWAHITO

702-709
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Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits

Zheng LIU, Masanori FURUTA, Shoji KAWAHITO

710-716
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An Image Rejection Mixer with AI-Based Improved Performance for WCDMA Applications

Yuji KASAI, Kiyoshi MIYASHITA, Hidenori SAKANASHI, Eiichi TAKAHASHI, Masaya IWATA, Masahiro MURAKAWA, Kiyoshi WATANABE, Yukihiro UEDA, Kaoru TAKASUKA, Tetsuya HIGUCHI

717-724
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True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalers

Sheng-Che TSENG, Chinchun MENG, Wei-Yu CHEN

725-731
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Extended Phase Noise Performance in Mutual Negative Resistance CMOS LC Oscillator for Low Supply Voltages

Apisak WORAPISHET

732-738
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A -90 dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit

Shiro DOSHO, Takashi MORIE, Koji OKAMOTO, Yuuji YAMADA, Kazuaki SOGAWA

739-745
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A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector

Ching-Yuan YANG, Yu LEE, Cheng-Hsing LEE

746-752
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All-Digital Clock Deskew Buffer with Variable Duty Cycles

Shao-Ku KAO, Shen-Iuan LIU

753-760
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An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity

Koichiro NOGUCHI, Makoto NAGATA

761-768
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A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique

Takeshi YOSHIDA, Yoshihiro MASUI, Takayuki MASHIMO, Mamoru SASAKI, Atsushi IWATA

769-774
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Modified CMOS Op-Amp with Improved Gain and Bandwidth

Mahdi MOTTAGHI- KASHTIBAN, Khayrollah HADIDI, Abdollah KHOEI

775-780
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An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture

Osamu NOMURA, Takashi MORIE, Keisuke KOREKADO, Teppei NAKANO, Masakazu MATSUGU, Atsushi IWATA

781-791
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MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm

Chia-Chi CHU, Ming-Hong LAI, Wu-Shiung FENG

792-802
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A Method Using an Averaging Technique for the Analysis and Evaluation of Real Quasi-Resonant Converters

Yi-Cherng LIN, Der-Cherng LIAW

803-810
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Extended-Range High-Resolution FMCW Reflectometry by Means of Electronically Frequency-Multiplied Sampling Signal Generated from Auxiliary Interferometer

Koichi IIYAMA, Makoto YASUDA, Saburo TAKAMIYA

823-829
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Numerical Investigation of Octagonal Photonic Crystal Fibers with Strong Confinement Field

Kenta KANESHIMA, Yoshinori NAMIHIRA, Nianyu ZOU, Hiroki HIGA, Yasunori NAGATA

830-837
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A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era

Kazutoshi KOBAYASHI, Akihiko HIGUCHI, Hidetoshi ONODERA

838-843
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Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications

Yasuo SUGURE, Seiji TAKEUCHI, Yuichi ABE, Hiromichi YAMADA, Kazuya HIRAYANAGI, Akihiko TOMITA, Kesami HAGIWARA, Takeshi KATAOKA, Takanori SHIMURA

844-850
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A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range ΣΔ Modulator

Yi-Bin HSIEH, Yao-Huang KAO

851-857
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Invited Papers

Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use

Masao HOTTA, Tatsuji MATSUURA

664-672
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Ultra-Low Voltage Analog Integrated Circuits

Shouri CHATTERJEE, Yannis TSIVIDIS, Peter KINGET

673-680
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RF Passive Components Using Metal Line on Si CMOS

Kazuya MASU, Kenichi OKADA, Hiroyuki ITO

681-691
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