Vol. E89-C, No. 3 March 2006

Foreword

FOREWORD

Akira MATSUZAWA

211-212
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Letters

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI

Danardono Dwi ANTONO, Kenichi INAGAKI, Hiroshi KAWAGUCHI, Takayasu SAKURAI

392-394
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A New Approach to Mixed-Path Propagation of Surface Wave

Bin-hao JIANG

434-436
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Quantum Noise and Feed-Back Noise in Blue-Violet InGaN Semiconductor Lasers

Kenjiro MATSUOKA, Kazushi SAEKI, Eiji TERAOKA, Minoru YAMADA, Yuji KUWAMURA

437-439
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Low Power Low Phase Noise LC Quadrature VCO Topology

Ji-Hoon KIM, Hyung-Joun YOO

440-442
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Papers

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation

Noriyuki MINEGISHI, Junichi MIYAKOSHI, Yuki KURODA, Tadayoshi KATAGIRI, Yuki FUKUYAMA, Ryo YAMAMOTO, Masayuki MIYAMA, Kousuke IMAMURA, Hideo HASHIMOTO, Masahiko YOSHIMOTO

230-242
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A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier

Jumpei UCHIDA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI

243-249
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Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits

Nobuaki KOBAYASHI, Tomomi EI, Tadayoshi ENOMOTO

271-279
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Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_TH/V_DD and Micro-V_DD-Hopping

Canh Quang TRAN, Hiroshi KAWAGUCHI, Takayasu SAKURAI

280-286
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Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core

Tetsuya YAMADA, Masahide ABE, Yusuke NITTA, Kenji OGURA, Manabu KUSAOKE, Makoto ISHIKAWA, Motokazu OZAWA, Kiwamu TAKADA, Fumio ARAKAWA, Osamu NISHII, Toshihiro HATTORI

287-294
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A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology

Chi-Nan CHUANG, Shen-Iuan LIU

295-299
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Channel-Count-Independent BIST for Multi-Channel SerDes

Kouichi YAMAGUCHI, Muneo FUKAISHI

314-319
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A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology

Daisuke MIZOGUCHI, Noriyuki MIURA, Takayasu SAKURAI, Tadahiro KURODA

320-326
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Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect

Yoichi YUYAMA, Akira TSUCHIYA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA

327-333
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An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques

Masahiro NOMURA, Taku OHSAWA, Koichi TAKEDA, Yoetsu NAKAZAWA, Yoshinori HIROTA, Yasuhiko HAGIHARA, Naoki NISHI

334-341
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A Statistical Quality Model for Delay Testing

Yasuo SATO, Shuji HAMADA, Toshiyuki MAEDA, Atsuo TAKATORI, Seiji KAJIHARA

349-355
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Multi-Ported Register File for Reducing the Impact of PVT Variation

Yuuichirou IKEDA, Masaya SUMITA, Makoto NAGATA

356-363
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Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply

Toru NAKURA, Makoto IKEDA, Kunihiro ASADA

364-369
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On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function

Mohamed ABBAS, Makoto IKEDA, Kunihiro ASADA

370-376
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Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment

Makoto SUGIHARA, Taiga TAKATA, Kenta NAKAMURA, Ryoichi INANAMI, Hiroaki HAYASHI, Katsumi KISHIMOTO, Tetsuya HASEBE, Yukihiro KAWANO, Yusuke MATSUNAGA, Kazuaki MURAKAMI, Katsuya OKUMURA

377-383
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Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond

Yoshihide KOMATSU, Yukio ARIMA, Koichiro ISHIBASHI

384-391
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Propagation Analysis of Circular Surface Waveguides with a Periodically Corrugated Ground Plane

Chin-Jui LAI, Ching-Her LEE, Chung-I G. HSU, Jean-Fu KIANG

395-402
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Aperture-Backed Microstrip-Line Stepped-Impedance Resonators and Transformers for Performance-Enhanced Bandpass Filters

Hang WANG, Lei ZHU

403-409
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Extraction of LRGC Matrices for 8-Coupled Uniform Lossy Transmission Lines Using 2-Port VNA Measurements

Hyun Bae LEE, Kyoungho LEE, Hae Kang JUNG, Hong June PARK

410-419
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A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications

Kang-Yoon LEE, Hyunchul KU, Young Beom KIM

420-428
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Evaluation of the Fusional Limit between the Front and Rear Images in Depth-Fused 3-D Visual Illusion

Hideaki TAKADA, Shiro SUYAMA, Munekazu DATE

429-433
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Invited Papers

System LSI: Challenges and Opportunities

Tadahiro KURODA

213-220
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Design Philosophy of a Networking-Oriented Data-Driven Processor: CUE

Hiroaki NISHIKAWA

221-229
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Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond

Koichiro ISHIBASHI, Tetsuya FUJIMOTO, Takahiro YAMASHITA, Hiroyuki OKADA, Yukio ARIMA, Yasuyuki HASHIMOTO, Kohji SAKATA, Isao MINEMATSU, Yasuo ITOH, Haruki TODA, Motoi ICHIHASHI, Yoshihide KOMATSU, Masato HAGIWARA, Toshiro TSUKADA

250-262
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Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI

Yukihito OOWAKI, Shinichiro SHIRATAKE, Toshihide FUJIYOSHI, Mototsugu HAMADA, Fumitoshi HATORI, Masami MURAKATA, Masafumi TAKAHASHI

263-270
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Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies

Hirotaka TAMURA, Masaya KIBUNE, Hisakatsu YAMAGUCHI, Kouichi KANDA, Kohtaroh GOTOH, Hideki ISHIDA, Junji OGAWA

300-313
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Variability: Modeling and Its Impact on Design

Hidetoshi ONODERA

342-348
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Foreword

FOREWORD

Letters

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI

A New Approach to Mixed-Path Propagation of Surface Wave

Quantum Noise and Feed-Back Noise in Blue-Violet InGaN Semiconductor Lasers

Low Power Low Phase Noise LC Quadrature VCO Topology

Papers

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier

Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_TH/V_DD and Micro-V_DD-Hopping

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core

A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology

Channel-Count-Independent BIST for Multi-Channel SerDes

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect

An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques

A Statistical Quality Model for Delay Testing

Multi-Ported Register File for Reducing the Impact of PVT Variation

Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply

On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment

Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond

Propagation Analysis of Circular Surface Waveguides with a Periodically Corrugated Ground Plane

Aperture-Backed Microstrip-Line Stepped-Impedance Resonators and Transformers for Performance-Enhanced Bandpass Filters

Extraction of LRGC Matrices for 8-Coupled Uniform Lossy Transmission Lines Using 2-Port VNA Measurements

A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications

Evaluation of the Fusional Limit between the Front and Rear Images in Depth-Fused 3-D Visual Illusion

Invited Papers

System LSI: Challenges and Opportunities

Design Philosophy of a Networking-Oriented Data-Driven Processor: CUE

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies

Variability: Modeling and Its Impact on Design

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