A 90 nm 48<img src="/img_font/cd0215f.gif" border="0">48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations

Authors

Kazutoshi KOBAYASHI
Kazuya KATSUKI
Manabu KOTANI
Yuuri SUGIHARA
Yohei KUME
Hidetoshi ONODERA

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Published

2007-10-01

Issue

Vol. E90-C, No. 10 October 2007

Section

Papers