Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation

Authors

• Noriaki ODA
• Hironori IMURA
• Naoyoshi KAWAHARA
• Masayoshi TAGAMI
• Hiroyuki KUNISHIMA
• Shuji SONE
• Sadayuki OHNISHI
• Kenta YAMADA
• Yumi KAKUHARA
• Makoto SEKINE
• Yoshihiro HAYASHI
• Kazuyoshi UENO