TOML Transistor Operations for Machine Learning

A Physics-Grounded Energy Efficiency Framework

Abstract

The escalating energy consumption of machine learning systems demands accurate, physics-grounded efficiency measurement
beyond conventional proxies like FLOPs and MACs, which fail to capture non-linear operations and memory access costs. While recent work established transistor operations (TOs) as a promising energy proxy for convolutional neural networks, this approach remains limited to a single metric and narrow architectural scope. We present TOML (Transistor Operations for Machine Learning), a framework introducing six novel metrics grounded in CMOS physics: Switching Activity Factor per Token (SAF-T), Logic State Residence Time (LSRT), Energy per Capability Unit (ECU), Memory-Compute Energy Ratio (MCER), Data-Dependent Energy Variation (DDEV), and Capability-per-Transistor-Operation (CpTO). TOML extends transistor-level energy modeling to CNNs, RNNs, LSTMs, and gradient boosting architectures through architecture-specific β-coefficients derived from fundamental semiconductor physics. Validated across seven architectures on both CPU and GPU hardware, TOML achieves r2 = 0.961 correlation with measured energy on CPU, a 49.6% improvement over FLOP-based estimation. Our metrics reveal that tested architectures are predominantly memory-bound (MCER > 1), with substantial efficiency variation within architecture families: 9.5× among accuracy-evaluated models and 6.5× among perplexity-evaluated sequence models when normalized by capability. Unlike prior approaches, TOML captures data-dependent energy variation (16–33% for CNNs) and provides capability-normalized metrics enabling fair cross-architecture comparison.